Implementation of the Cluster based Tunable Sleep Transistor Cell Power Gating Technique for a 4×4 Multiplier Circuit

نویسندگان

  • Dipankar Saha
  • Subhramita Basak
  • Sagar Mukherjee
  • Sayan Chatterjee
  • C. K. Sarkar
  • Ehsan Pakbaznia
  • Massoud Pedram
  • A. Sathanur
  • A. Pullini
  • L. Benini
  • A. Macii
  • E. Macii
  • L. M. L. Silva
  • A. Calimera
چکیده

A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc. ; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage

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Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit

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تاریخ انتشار 2016